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Provisional Data Sheet No. PD - 9.1719
IRFE430 REPETITIVE AVALANCHE AND dv/dt RATED JANTX2N6802U (R) HEXFET TRANSISTOR JANTXV2N6802U [REF:MIL-PRF-19500/557]
N-CHANNEL 500Volt, 1.50, HEXFET
The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. The LCC provides designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. HEXFET transistors also feature all of the well-established advantages of MOSFETs, such as voltage control, very fast switching, ease of paralleling and electrical parameter temperature stability. They are well-suited for applications such as switching power supplies, motor controls, inverters, choppers, audio amplifiers and high-energy pulse circuits, and virtually any application where high reliability is required.
Product Summary
Part Number IRFE430 BVDSS 500V RDS(on) 1.50 ID 2.5A
Features:
n n n n n n
Hermetically Sealed Simple Drive Requirements Ease of Paralleling Small footprint Surface Mount Lightweight
Absolute Maximum Ratings
Parameter
ID @ VGS = 10V, TC = 25C ID @ VGS = 10V, TC = 100C IDM PD @ TC = 25C VGS EAS dv/dt TJ TSTG Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Surface Temperature Weight IRFE430, JANTX-, JANTXV-, 2N6802U Units 2.5 A 1.5 11 25 W 0.20 W/K 20 V 0.31 mJ 6.2 V/ns -55 to 150
o
C
300 ( for 5 seconds) 0.42 (typical)
g
12/3097
IRFE430, JANTX-, JANTXV-, 2N6802U Device
Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified)
Parameter
BVDSS Drain-to-Source Breakdown Voltage BVDSS/TJ Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS Zero Gate Voltage Drain Current
Min
500 -- -- -- 2.0 2.0 -- -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- 0.59 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.8 4.3 -- -- 1.50 1.725 4.0 -- 25 250 100 -100 30 4.5 28 30 30 55 30 -- -- V V/C V S( ) A
Test Conditions
VGS =0 V, ID = 1.0mA Reference to 25C, ID = 1.0mA VGS = 10V, ID = 1.5A VGS = 10V, ID = 2.5A V DS = VGS, ID = 250A VDS > 15V, I DS = 1.5A VDS= 0.8 x Max Rating,VGS=0V VDS = 0.8 x Max Rating VGS = 0V, TJ = 125C VGS = 20 V VGS = -20V VGS = 10V, ID = 2.5A VDS = Max Rating x 0.5 VDD = 250V, ID = 2.5A, RG = 7.5
IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance
nA nC
ns
Measured from drain pad to die.
Modified MOSFET symbol showing the internal inductances.
nH
Measured from center of source pad to the end of source bonding wire.
Ciss Coss Crss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
-- -- --
750 240 67
-- -- --
pF
VGS = 0V, VDS = 25 V f = 1.0MHz
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD trr QRR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- 2.5 11 1.4 900 2.0
Test Conditions
Modified MOSFET symbol showing the integral reverse p-n junction rectifier. Tj = 25C, IS = 2.5A, VGS = 0V Tj = 25C, IF = 2.5A, di/dt 100A/s VDD 50V
A
V ns C
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC RthJPCB Junction-to-Case Junction-to-PC Board
Min Typ Max
-- -- -- -- 5.0
Units
K/W
Test Conditions
19
Soldered to a copper clad PC board
Details of notes 2
through are on the last page www.irf.com
IRFE430, JANTX-, JANTXV-, 2N6802U Device
100
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
10
4.5V
1
1
4.5V
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 0.1
0.1 1 10
20s PULSE WIDTH TJ = 150 C
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
ID = 2.5A
I D , Drain-to-Source Current (A)
2.5
10
2.0
TJ = 150 C
1.5
TJ = 25 C
1
1.0
0.5
0.1 4.0
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
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Fig 4. Normalized On-Resistance Vs. Temperature
3
IRFE430, JANTX-, JANTXV-, 2N6802U Device
1600
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = 2.5A VDS = 400V VDS = 250V VDS = 100V
16
1200
C, Capacitance (pF)
Ciss
800
12
8
Coss
400
Crss
0 1 10 100
4
0 0 5 10 15
FOR TEST CIRCUIT SEE FIGURE 13
20 25 30
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
10
100
OPERATION IN THIS AREA LIMITED BY RDS(on)
ISD , Reverse Drain Current (A)
TJ = 150 C
I D , Drain Current (A)
10 10us
1
100us 1 1ms
TJ = 25 C
0.1 0.4
V GS = 0 V
0.6 0.8 1.0
0.1
TC = 25 C TJ = 150 C Single Pulse
10 100
10ms
1000
10000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
4
Fig 8. Maximum Safe Operating Area
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IRFE430, JANTX-, JANTXV-, 2N6802U Device
2.5
VDS VGS
RD
2.0
D.U.T.
+
RG
I D , Drain Current (A)
-VDD
1.5
10V
Pulse Width 1 s Duty Factor 0.1 %
1.0
Fig 10a. Switching Time Test Circuit
0.5
VDS 90%
0.0 25 50 75 100 125 150
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 0.20 0.10 0.05 0.02 0.1 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 10
1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFE430, JANTX-, JANTXV-, 2N6802U Device
0.80
EAS , Single Pulse Avalanche Energy (mJ)
TOP BOTTOM
0.60
1 5V
ID 1.1A 1.6A 2.5A
VDS
L
D R IV E R
RG
10V 20V
D .U .T
IA S tp
0.40
+ - VD D
A
0 .0 1
0.20
Fig 12a. Unclamped Inductive Test Circuit
0.00 25 50 75 100 125 150
V (B R )D SS tp
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
10V 12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
6
Fig 13b. Gate Charge Test Circuit
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IRFE430, JANTX-, JANTXV-, 2N6802U Device
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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IRFE430, JANTX-, JANTXV-, 2N6802U Device
Notes:
Repetitive Rating; Pulse width limited by @ VDD = 50 V, Starting TJ = 25C, ISD 2.5A, di/dt 86 A/s,
VDD BVDSS , TJ 150C Suggested RG = 2.35 maximum junction temperature. EAS = [0.5 * L * (IL2) ] Refer to current HEXFET reliability report. Peak IL = 2.5A, VGS =10 V, 25 RG 200 Pulse width 300 s; Duty Cycle 2% K/W = C/W
Case Outline and Dimensions -- Leadless Chip Carrier (LCC) Package
IR Case Style Leadless Chip Carrier (LCC)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 12/97
8
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